कम्प्युटर / सूचना प्रविधि कम्प्युटर अधिकृत (सातौँ तह) – प्राविधिक पत्र
कम्प्युटर / सूचना प्रविधि – कम्प्युटर अधिकृत (सातौँ तह)
Computer Officer – 7th Level · Computer & IT Posts
१,५०२ प्रश्न उपलब्ध। मोड छान्नुहोस्:
प्राविधिक पत्र: प्रश्न र उत्तर
सही लागेको विकल्पमा थिच्नुहोस्। सही भए हरियो, गलत भए रातो देखिन्छ; ५ सेकेन्डपछि सही उत्तर र व्याख्या देखिन्छ।
सही: ० / ०
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The contents of a mask ROM are written:
सही उत्तर: ख) during manufacturing, using a photomask
Mask ROM data is built into the chip during fabrication, so it is economical only for large production runs.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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A PROM (Programmable ROM) chip can be programmed by the user:
सही उत्तर: क) only once
A PROM is written once by blowing internal fuses; it cannot be erased afterwards.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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An SRAM cell stores one bit using:
सही उत्तर: घ) a flip-flop made of transistors (typically six)
SRAM uses a bistable latch, so it holds data as long as power is on without needing refresh.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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A 4-stage pipeline has each stage taking 10 ns. With no stalls, the time to complete 10 instructions is:
सही उत्तर: ख) 130 ns
Time = (k + n - 1) x t = (4 + 10 - 1) x 10 ns = 130 ns.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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In DMA, the method in which the DMA controller takes the system bus for one cycle at a time, in between CPU cycles, is called:
सही उत्तर: ख) cycle stealing
In cycle stealing the DMA controller transfers one word per stolen bus cycle, letting the CPU continue in between.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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When the CPU repeatedly checks each I/O device to see whether it needs service, the technique is called:
सही उत्तर: ख) polling
In polling (programmed I/O) the CPU tests status flags itself, wasting time compared with interrupts.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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A structural hazard in a pipeline occurs when:
सही उत्तर: क) two instructions need the same hardware resource in the same clock cycle
For example, a single memory port needed by both an instruction fetch and a data access causes a structural hazard.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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In a pipelined processor, a data hazard occurs when:
सही उत्तर: क) an instruction needs the result of an earlier instruction that is still in the pipeline
For example, ADD R1,R2,R3 followed by SUB R4,R1,R5 needs R1 before the ADD has written it back.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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A processor runs at 2 GHz with an average of 4 clock cycles per instruction. Its speed in MIPS is:
सही उत्तर: ख) 500
MIPS = clock rate / (CPI x 10^6) = 2000 MHz / 4 = 500 MIPS.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
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An instruction like CMA (complement the accumulator) in the 8085, whose operand is specified by the opcode itself, uses which addressing mode?
सही उत्तर: क) Implied (implicit) addressing
In implied addressing the operand (here the accumulator) is understood from the opcode, so no operand field is needed.
💬 टिप्पणी / गल्ती रिपोर्ट (०)
यी अभ्यास प्रश्न हुन्, आधिकारिक प्रश्न होइनन्। पाठ्यक्रम, विज्ञापन र नतिजाका लागि सम्बन्धित निकायको आधिकारिक वेबसाइट हेर्नुहोस्। उत्तरमा गल्ती भेटे प्रश्नमुनिको "टिप्पणी / गल्ती रिपोर्ट" मा लेख्नुहोस्।
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